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19-5333; Rev 0; 6/10
TION KIT EVALUA BLE AVAILA
24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface
General Description
The MAX11201 is an ultra-low-power (< 320FA max active current), high-resolution, serial-output ADC. This device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11201 provides a high-accuracy internal oscillator that requires no external components. When used with the specified data rates, the internal digital filter provides more than 100dB rejection of 50Hz or 60Hz line noise. The MAX11201 provides a simple 2-wire serial interface in the space-saving, 10-pin FMAXM package. The MAX11201 operates over the -40NC to +85NC temperature range.
Features
S 23.3-Bit ENOB 20.6-Bit Noise-Free Resolution at 13.75sps 19.1-Bit Noise-Free Resolution at 120sps S 700nVRMS Noise 3.6VFS Input (MAX11201B) S INL: 3ppm (typ), 10ppm (max) S No Missing Codes S Ultra-Low Power Dissipation Operating Mode Current Drain < 320A (max) Sleep Mode Current Drain < 0.4A S 2.7V to 3.6V Analog Supply Voltage Range S 1.7V to 3.6V Digital and I/O Supply Voltage Range S Fully Differential Signal and Reference Inputs S High-Impedance Inputs Buffers on Signal Inputs S Programmable Internal System Clock or External Clock 2.4576MHz (MAX11201A) 2.25275MHz (MAX11201B) S > 100dB (min) 50Hz/60Hz Rejection (MAX11201B) S Serial 2-Wire Interface (Clock Input and Data Output) S On-Demand Offset and Gain Self-Calibration S -40C to +85C Operating Temperature Range S 2kV ESD Protection S Lead(Pb)-Free and RoHS-Compliant MAX Package
MAX11201
Applications
Sensor Measurement (Temperature and Pressure) Portable Instrumentation Battery Applications Weigh Scales
Ordering Information
PART MAX11201AEUB+ MAX11201BEUB+ PIN-PACKAGE 10 FMAX 10 FMAX OUTPUT RATE (sps) 120 13.75
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
4-WIRE SPI, 16-PIN QSOP MAX11200 MAX11207 MAX11211 MAX11203 2-WIRE SERIAL, 10-PIN MAX MAX11201 (with buffers) MAX11202 (without buffers) MAX11208 MAX11212 MAX11205
RESOLUTION (BITS) 24 20 18 16
4-WIRE SPI, 16-PIN QSOP, PROGRAMMABLE GAIN MAX11210 MAX11206 MAX11209 MAX11213
MAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND ....................................................-0.3V to +3.9V AVDD to GND.......................................................-0.3V to +3.9V DVDD to GND ......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND.............................................. -0.3V to (VAVDD + 0.3V) Digital Inputs and Digital Outputs to GND.............................................. -0.3V to (VDVDD + 0.3V) ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK, RDY/DOUT, GND) ............................................ Q2kV (Note 1) Continuous Power Dissipation (TA = +70NC) 10-Pin FMAX (derate 5.6mW/NC above +70NC) ..........444mW Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -55NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER ADC PERFORMANCE Noise-Free Resolution (Notes 2, 3) Noise (Notes 2, 3) Integral Nonlinearity Zero Error Zero Drift Full-Scale Error Full-Scale Error Drift Power-Supply Rejection ANALOG INPUTS/REFERENCE INPUTS DC rejection Common-Mode Rejection Normal-Mode 50Hz Rejection Normal-Mode 60Hz Rejection Common-Mode Voltage Range Low input voltage Absolute Input Voltage High input voltage DC Input Leakage Sleep mode (Note 2) CMR NMR50 NMR60 50Hz/60Hz rejection, MAX11201A 50Hz/60Hz rejection, MAX11201B MAX11201B (Note 6) MAX11201B (Note 6) 90 90 144 100 100 GND VGND + 100mV VAVDD 100mV Q1 144 144 VAVDD dB dB V 123 dB AVDD DC rejection DVDD DC rejection 70 90 After calibration, VREFP - VREFN = 2.5V (Note 5) -20 0.05 80 100 NFR VN INL VOFF MAX11201A MAX11201B MAX11201A MAX11201B (Note 4) After calibration, VREFP - VREFN = 2.5V -10 -10 50 +20 19.1 20.6 2.0 0.70 +10 +10 Bits FVRMS ppmFSR ppmFSR nV/NC ppmFSR ppmFSR/ NC dB SYMBOL CONDITIONS MIN TYP MAX UNITS
V
FA
2
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER AIN_ Dynamic Input Current REF_ Dynamic Input Current AIN_ Input Capacitance REF_ Input Capacitance AIN_ Voltage Range REF_ Voltage Range Input Sampling Rate REF Sampling Rate LOGIC INPUTS (SCLK, CLK) Input Current Input Low Voltage Input High Voltage Input Hysteresis External Clock LOGIC OUTPUT (RDY/DOUT) Output Low Level Output High Level Leakage Current Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Total Operating Current DVDD Operating Current AVDD Operating Current AVDD Sleep Current DVDD Sleep Current 2-WIRE SERIAL-INTERFACE TIMING CHARACTERISTICS SCLK Frequency SCLK Pulse Width Low SCLK Pulse Width High SCLK Rising Edge to Data Valid Transition Time fSCLK t1 t2 t3 60/40 duty cycle, 5MHz clock 40/60 duty cycle, 5MHz clock 80 80 40 5 MHz ns ns ns AVDD DVDD AVDD + DVDD 2.7 1.7 245 50 195 0.15 0.25 3.6 3.6 320 60 265 2 2 V V FA FA FA FA FA VOL VOH IOL = 1mA; also tested for VDVDD = 3.6V IOH = 1mA; also tested for VDVDD = 3.6V High-impedance state High-impedance state 0.9 x VDVDD Q10 9 0.4 V V FA pF VIL VIH VHYS MAX11201A MAX11201B 0.7 x VDVDD 200 2.4576 2.25275 Input leakage current Q1 0.3 x VDVDD FA V V mV MHz fS MAX11201A MAX11201B MAX11201A MAX11201B AINP - AINN -VREF 0 246 225 246 225 SYMBOL CONDITIONS MIN TYP 20 30 5 7.5 +VREF VAVDD MAX UNITS nA nA pF pF V V kHz kHz
MAX11201
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SCLK Rising Edge Data Hold Time RDY/DOUT Fall to SCLK Rising Edge Next Data Update Time; No Read Allowed Data Conversion Time Data Ready Time After Calibration Starts (CAL + CNV) SCLK High After RDY/DOUT Goes Low to Activate Sleep Mode Time from RDY/DOUT Low to SCLK High for Sleep-Mode Activation Data Ready Time After Wake-Up From Sleep Mode Data Ready Time After Calibration From Sleep Mode Wake-Up (CAL + CNV) Note Note Note Note Note 2: 3: 4: 5: 6: SYMBOL t4 t5 t6 t7 t8 t9 t10 t11 t12 MAX11201A MAX11201B MAX11201A MAX11201B MAX11201A MAX11201B MAX11201A MAX11201B MAX11201A MAX11201B MAX11201A MAX11201B MAX11201A MAX11201B 0 0 0 0 8.6 73 208.4 256.2 CONDITIONS Allows for positive edge data read MIN 3 0 155 169 8.6 73 208.3 256.1 8.6 73 8.6 73 TYP MAX UNITS ns ns Fs ms ms ms ms ms ms
These specifications are not fully tested and are guaranteed by design and/or characterization. VAINP = VAINN. ppmFSR is parts per million of full-scale range. Positive full-scale error includes zero-scale errors. The MAX11201A has no normal-mode rejection at 50Hz or 60Hz.
4
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11201A)
MAX11201 toc01
MAX11201
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11201B)
220 200 CURRENT (A) CURRENT (A) 180 160 140 120 100 0.2 TA = +25C 0.6 0.4
MAX11201 toc02
ANALOG SLEEP CURRENT vs. AVDD VOLTAGE
MAX11201 toc03
240 220 200 CURRENT (A) 180 160 140 120 100 2.70 2.85 3.00 3.15 3.30 3.45 TA = -45C TA = +85C TA = +25C
240 TA = +85C
1.0 0.8
TA = -45C
TA = +25C 0 2.70 2.85 3.00 3.15 3.30 3.45 3.60
TA = +85C
TA = -45C
3.60
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD VOLTAGE (V)
AVDD VOLTAGE (V)
AVDD VOLTAGE (V)
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11201A)
MAX11201 toc04
ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11201B)
MAX11201 toc05
SLEEP CURRENT vs. TEMPERATURE
VAVDD = 3.0V 0.8
CURRENT (A)
MAX11201 toc06
300 250 200 150 100 50 0 -45 -25 -5 15 35 55 75 VDVDD = 1.8V TOTAL VAVDD = 3.0V
300 250 200 150 100 50 0 VDVDD = 1.8V
1.0
TOTAL VAVDD = 3.0V
CURRENT (A)
CURRENT (A)
0.6 0.4 0.2 0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C) DVDD TOTAL
AVDD
95
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
TEMPERATURE (C)
DIGITAL ACTIVE CURRENT vs. DVDD VOLTAGE
MAX11201 toc07
DIGITAL SLEEP CURRENT vs. DVDD VOLTAGE
MAX11201 toc08
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
VAVDD = 3.0V MAX11201A
MAX11201 toc09
130 120 110
CURRENT (A)
TA = +85C, +25C, -45C
3.0 2.5 2.0 1.5 1.0 0.5 0 TA = +85C TA = -45C TA = +25C
2.6 2.5
FREQUENCY (MHz)
90 80 70 60 50 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD VOLTAGE (V) MAX11201B
CURRENT (A)
100
MAX11201A
2.4 2.3 2.2 2.1 2.0 MAX11201B
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 DVDD VOLTAGE (V)
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.)
INTERNAL OSCILLATOR FREQUENCY vs. AVDD VOLTAGE
MAX11201 toc10
NOISE vs. INPUT VOLTAGE
MAX11201 toc11
NOISE vs. TEMPERATURE
3.5 3.0 NOISE (VRMS) 2.5 2.0 1.5 1.0 0.5 0
MAX11201B MAX11201A VREF = 3.0V
MAX11201 toc12
2.6 2.5 FREQUENCY (MHz) 2.4 2.3 2.2 2.1 2.70 2.85 3.00 3.15 3.30 3.45
4.0 3.5 3.0 NOISE (VRMS) 2.5 2.0 1.5 1.0 0.5 MAX11201B VREF = 2.5V
4.0
MAX11201A
MAX11201A
MAX11201B
3.60
0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V)
-45
-25
AVDD VOLTAGE (V)
-5 15 35 55 TEMPERATURE (C)
75
95
NOISE HISTOGRAM (MAX11201A, 120sps)
MAX11201 toc13
NOISE HISTOGRAM (MAX11201B, 13.75sps)
MAX11201 toc14
LONG-TERM ADC READINGS (MAX11201A)
TA = +25C VIN = 0V RMS = 2.1V
MAX11201 toc15
14 30,000 CONSECUTIVE READINGS 12 NUMBER OF READINGS (%) 10 8 6 4 2 0 -2.7 -0.3 2.0 4.3 6.7 9.0 11.3 ADC OUTPUT (V) TA = +25C VREF = 2.5V RMS = 2.1V MEAN = 5.0V
20 18 NUMBER OF READINGS (%) 16 14 12 10 8 6 4 2 0 1.19 2.04 2.89 3.74 4.59 5.44 6.29 ADC OUTPUT (V) 30,000 CONSECUTIVE READINGS TA = +25C VREF = 2.5V RMS = 0.72V MEAN = 4.1V
15 10 ADC READING (V) 5 0 -5 -10 -15 0 0.2 0.4 0.6 0.8
1.0
TIME (MINUTES)
LONG-TERM ADC READINGS (MAX11201B)
MAX11201 toc16
OFFSET ERROR vs. VREF
MAX11201 toc17
OFFSET ERROR vs. TEMPERATURE
CALIBRATED AT +25C
MAX11201 toc18
5 4 3
ADC READING (V)
TA = +25C VIN = 0V RMS = 0.70V
2.0 1.5 OFFSET ERROR (ppmFSR) 1.0 0.5
2.5 2.0 1.5 1.0 0.5 0
VREF = VREFP - VREFN TA = +25C
2 1 0 -1 -2 -3 -4 -5 0 2 4 6 8 10 TIME (MINUTES)
TA = +85C 0 -0.5 -1.0 1.0 1.5 2.0
TA = -45C
OFFSET ERROR (ppmFSR)
2.5 VREF (V)
3.0
3.5
4.0
-45
-25
-5
15
35
55
75
95
TEMPERATURE (C)
6
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25NC.)
INL vs. INPUT VOLTAGE
MAX11201 toc19
MAX11201
TUE vs. INPUT VOLTAGE
MAX11201 toc20
FULL-SCALE ERROR vs. TEMPERATURE
NORMALIZED FULL-SCALE ERROR (ppmFSR) 8 6 4 2 0 -2 -4 -6 -8 -10 -45 -25 -5 15 35 55 75 TEMPERATURE (C) -FS ERROR +FS ERROR VREF = 2.5V
MAX11201 toc21 MAX11201 toc24
10 8 6 4
INL (ppmFSR)
10 8 6 4 INL (ppmFSR) 2 0 -2 -4 -6 -8 -10
VIN(CM) = 1.8V TA = -45C
VIN(CM) = 1.8V
10
2 0 -2 -4 -6 -8 -10 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V) TA = +85C TA = +25C
TA = +25C TA = +85C
TA = -45C
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
PSRR vs. FREQUENCY (MAX11201A)
MAX11201 toc22
PSRR vs. FREQUENCY (MAX11201B)
MAX11201 toc23
CMRR vs. FREQUENCY
0 -20 -40 CMRR (dB) -60 -80 -100 MAX11201A
0 -20 -40 PSRR (dB) -60 -80 -100 DVDD -120 -140 1 10 100 1000 AVDD
0 -20 -40 PSRR (dB) -60 -80 -100 -120 -140 1 10 100 1000 DVDD AVDD
-120 -140 10,000 100,000 1 10
MAX11201B 100 1000 10,000 100,000
10,000 100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
NORMAL-MODE REJECTION DATA RATE 120.0SPS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150
MAX11201 toc25
NORMAL-MODE REJECTION DATA RATE 13.750SPS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150
MAX11201 toc26
MAX11201A
MAX11201B
GAIN (dB)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
GAIN (dB)
0
10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz)
FREQUENCY (Hz)
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
Pin Configuration
TOP VIEW +
GND 1 REFP REFN AINN AINP 2 3 4 5 10 CLK 9 8 7 6 SCLK RDY/DOUT DVDD AVDD
MAX11201
MAX
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME GND REFP REFN AINN AINP AVDD DVDD RDY/DOUT SCLK CLK FUNCTION Ground. Ground reference for analog and digital circuitry. Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND. Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a voltage between AVDD and GND. Negative Fully Differential Analog Input Positive Fully Differential Analog Input Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND. Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND. Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial data output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/ DOUT changes on the rising edge of SCLK. Serial Clock Input. Apply an external serial clock to SCLK. External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock. Use a 2.4576MHz oscillator (MAX11201A) or a 2.25275MHz oscillator (MAX11201B).
8
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface
Functional Diagram
TIMING CLOCK GENERATOR CLK
MAX11201
AVDD DVDD GND
AINP DIGITAL FILTER (SINC4) DIGITAL LOGIC AND SERIALINTERFACE CONTROLLER SCLK
AINN
3RD-ORDER DELTA-SIGMA MODULATOR
RDY/DOUT
REFP REFN
MAX11201
Detailed Description
The MAX11201 is an ultra-low-power (< 245FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11201 provides a high-accuracy internal oscillator, which requires no external components. When used with the specified data rates, the internal digital filter provides more than 100dB rejection of 50Hz or 60Hz line noise. The MAX11201 provides a simple, system-friendly, 2-wire serial interface in the space-saving, 10-pin FMAX package. The MAX11201 utilizes power-on reset (POR) supplymonitoring circuitry on both the digital supply (DVDD) and the analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. The MAX11201 performs a self-calibration operation as part of the startup initialization sequence whenever a digital POR is triggered. It is important to have a stable reference voltage available at the REFP and REFN pins to ensure an accurate calibration cycle. If the reference voltage is not stable during a POR event, the part should be calibrated once the reference has stabilized. The part can be programmed for calibration by using 26 SCLKs as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V and has 100mV of hysteresis. The analog POR trigger threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the POR. The analog supply (AVDD) and the digital supply (DVDD) pins should be bypassed using 0.1F capacitors placed as close as possible to the package pin. The MAX11201 includes signal input buffers capable of reducing the average input current from 1.4FA/V on the analog inputs to a constant 20nA. The MAX11201 analog inputs provide > 100MI input impedance for connecting directly to high-impedance sources. The MAX11201 accepts two analog inputs (AINP and AINN). The modulator input range is bipolar (-VREF to +VREF). The MAX11201 incorporates a highly stable internal oscillator that provides the system clock. The system clock runs the internal state machine and is trimmed to 2.4576MHz (MAX11201A) or 2.25275MHz (MAX11201B). The internal oscillator clock is divided down to run the digital and analog timing.
Buffers
Power-On Reset (POR)
Analog Inputs
Internal Oscillator
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
The MAX11201 provides differential inputs REFP and REFN for an external reference voltage. Connect the external reference directly across the REFP and REFN to obtain the differential reference voltage. The commonmode voltage range for VREFP and VREFN is between 0 and VAVDD. The differential voltage range for REFP and REFN is 1.25V to VAVDD. The MAX11201 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a SINC4 (sinx/x)4 response. When the device is operating in single-cycle conversion mode, the filter is reset at the end of the conversion cycle. When operating in continuous conversion latent mode, the filter is not reset. The SINC4 filter has a -3dB frequency equal to 24% of the data rate. The data output is clocked out on RDY/DOUT. D23 is the MSB and D0 is the LSB. The data format is always two's complement. In two's complement format, the most negative value is 0x800000 (VAINP - VAINN = -VREF), the midscale value is 0x000000 (AINP - AINN = 0), and the most positive value is 0x7FFFFF (VAINP - VAINN = VREF). Any input exceeding the available input range is limited to the minimum or maximum data value.
Reference
The MAX11201 communicates through a 2-wire interface, with a clock input and data output. The output rate is predetermined based on the package option (MAX11201A at 120sps and MAX11201B at 13.75sps).
Serial-Digital Interface
Digital Filter
The MAX11201 is compatible with the 2-wire interface and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial interface only allows for data to be read out through the RDY/DOUT output. Supply the serial clock to SCLK to shift the conversion data out. The RDY/DOUT is used to signal data ready, as well as reading the data out when SCLK pulses are applied. RDY/DOUT is high by default. The MAX11201 pulls RDY/DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at the SCLK input. On applying the clock pulses at SCLK, the RDY/DOUT outputs the conversion data on every SCLK positive edge. To monitor data availability, pull RDY/DOUT high after reading the 24 bits of data by supplying a 25th SCLK pulse. The different operational modes using this 2-wire interface are described in the following sections. Data Read Following Every Conversion The MAX11201 indicates conversion data availability, as well as the retrieval of data through the RDY/DOUT output. The RDY/DOUT output idles at the value of the last bit read unless a 25th SCLK pulse is provided, causing RDY/DOUT to idle high. The timing diagram for the data read is shown in Figure 1. Once a low is detected on RDY/DOUT, clock pulses at SCLK clock out the data. Data is shifted out MSB first and is in binary two's complement format. Once all the data has been shifted out, a 25th SCLK is required to pull the RDY/DOUT output back to the idle high state. See Figure 2. If the data is not read before the next conversion data is updated, the old data is lost, as the new data overwrites the old value.
2-Wire Interface
Data Output
Table 1. Output Data Format
INPUT VOLTAGE VAINP - VAINN VREF
1 VREF x 1 - 2 23 - 1
DIGITAL OUTPUT CODE 0x7FFFFF 0x7FFFFE
2 23 - 1 0 2 23 - 1 - VREF
VREF
0x000001 0x000000 0xFFFFFF
1 VREF x 1 - 23 2 - 1
-VREF
0x800001 0x800000
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
t5 SCLK t3 RDY/DOUT D23 D22 D0 t6 CONVERSION IS DONE DATA IS AVAILABLE t7 CONVERSION IS DONE DATA IS AVAILABLE 1 2 t1 t2 3 24 t4
Figure 1. Timing Diagram for Data Read After Conversion
SCLK
1
2
3
24
25 25TH SLK RISING EDGE PULLS RDY/DOUT HIGH
RDY/DOUT D23 CONVERSION IS DONE DATA IS AVAILABLE D22 D0
CONVERSION IS DONE DATA IS AVAILABLE
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
Data Read Followed by Self-Calibration To initiate self-calibration at the end of a data read, provide a 26th SCLK clock pulse. After reading the 24 bits of conversion data, a 25th positive edge on SCLK pulls the RDY/DOUT output back high, indicating the end of the data read. Provide a 26th SCLK clock pulse to initiate a self-calibration routine starting on the falling edge of the SCLK. A subsequent falling edge of RDY/DOUT indicates data availability at the end of calibration. The timing is illustrated in Figure 3. Data Read Followed by Sleep Mode The MAX11201 can be put into sleep mode to save power between conversions. To activate the sleep mode, idle the SCLK high any time after the RDY/DOUT output goes low (that is, after conversion data is available). It is
not required to read out all 24 bits before putting the part in sleep mode. Sleep mode is activated after the SCLK is held high (see Figure 4). The RDY/DOUT output is pulled high once the device enters sleep mode. To come out of the sleep mode, pull SCLK low. After the sleep mode is deactivated (when the device wakes up), conversion starts again and RDY/DOUT goes low, indicating the next conversion data is available (see Figure 4). Single-Conversion Mode For operating the MAX11201 in single-conversion mode, activate and deactivate sleep mode between conversions as described in the Data Read Followed by Sleep Mode section). Single-conversion mode reduces power consumption by shutting down the device when idle between conversions. See Figure 4.
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24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
CALIBRATION STARTS ON 26TH SCLK SCLK 1 2 3 24 25 26 1 2
RDY/DOUT D23 CONVERSION IS DONE DATA IS AVAILABLE D22 D0
25TH SCLK PULLS RDY/DOUT HIGH D23 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t8 D22
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
DEVICE ENTERS SLEEP MODE SCLK 1 2 t9 t10 RDY/DOUT D23 CONVERSION IS DONE DATA IS AVAILABLE D22 D0 3 24 SLEEP MODE
DEVICE EXITS OUT SLEEP MODE 1 2
D23 CONVERSION IS DONE DATA IS AVAILABLE t11
D22
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing
Single-Conversion Mode with Self-Calibration at Wake-Up The MAX11201 can be put in self-calibration mode immediately after wake-up from sleep mode. Self-calibration at wake-up helps to compensate for temperature or supply changes if the device is shut down for extensive periods. To automatically start self-calibration at the end of sleep mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th SCLK, keep it high for as long as shutdown is desired. Once SCLK is pulled back low, the device automatically performs a self-calibration and, when the data is ready, the RDY/DOUT output goes low. See Figure 5. This also achieves the purpose of single conversions with selfcalibration.
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_____________________________________________________________________________________
24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
25TH SCLK PULLS RDY/DOUT HIGH DEVICE ENTERS SLEEP MODE 25 26 SLEEP MODE DEVICE EXITS OUT SLEEP MODE AND STARTS CALIBRATION 1 2
SCLK
1
2
3 t10
24
RDY/DOUT D23 CONVERSION IS DONE DATA IS AVAILABLE D22 D0 D23 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t12 D22
Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up
IREF1 = K x IREF2 IREF2
Applications Information
See Figure 6 for the RTD temperature measurement circuit and Figure 7 for a resistive bridge measurement circuit.
REFP
Chip Information
PROCESS: BiCMOS
MAX11201
RREF IREF1 REFN AINP RRTD AINN GND
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 10 MAX PACKAGE CODE U10+2 OUTLINE NO. 21-0061 LAND PATTERN NO. 90-0330
Figure 6. RTD Temperature Measurement Circuit
AVDD REFP REFN AINP
MAX11201
AINN
Figure 7. Resistive Bridge Measurement Circuit ______________________________________________________________________________________ 13
24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11201
Revision History
REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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